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IAR Embedded Workbench for Arm 9.70.x

ADRL (ARM)

In this section:
Syntax
ADRL{condition} register,expression
Parameters

{condition}

Can be one of the following—EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, and AL.

register

The register to load.

expression

A register-relative expression that evaluates to an address that is not word-aligned within 64 Kbytes, or a word-aligned address within 256 Kbytes. Unresolved expressions (for example expressions that contain external labels, or labels in other sections) must be within 64 Kbytes. The address can be either before or after the address of the instruction.

Description

The ADRL pseudo-instruction loads a program-relative address into a register. It is similar to the ADR pseudo-instruction. ADRL can load a wider range of addresses than ADR because it generates two data processing instructions. ADRL always assembles to two instructions. Even if the address can be reached in a single instruction, a second, redundant instruction is produced. If the assembler cannot construct the address in two instructions, it generates an error message and the assembly fails.

Example
            name    armAdrL
            section MYCODE:CODE(2)

            arm
            adrl    r1,label+0x2345 ; Becomes "add r1,pc,#0x45"
                                    ;     and "add r1,r1,#0x2300"
            data
label       dc32    0

            end