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IAR Embedded Workbench for RISC-V 3.40

Conditional assembly directives

In this section:
Syntax

ELSE

ELSEIF condition

ENDIF

IF condition

Parameters

condition

One of these:

An absolute expression

The expression must not contain forward or external references, and any non-zero value is considered as true.

string1==string2

The condition is true if string1 and string2 have the same length and contents.

string1!=string2

The condition is true if string1 and string2 have different length or contents.

Description

Use the IF, ELSE, ELSEIF, and ENDIF directives to control the assembly process at assembly time. If the condition following the IF directive is not true, the subsequent instructions do not generate any code (that is, it is not assembled or syntax checked) until an ELSEIF condition is true or ELSE or ENDIF directive is found.

Use ELSEIF to introduce a new condition after an IF directive. Conditional assembly directives can be used anywhere in an assembly, but have their greatest use in conjunction with macro processing.

All assembler directives (except for END) as well as the inclusion of files can be disabled by the conditional directives. Each IF directive must be terminated by an ENDIF directive. The ELSE and ENDIF directives are optional, and if used, must be inside an IF...ENDIF block. IF...ENDIF and IF...ELSE...ENDIF blocks can be nested to any level.

Example

This example uses a macro to add a constant to a direct page memory location:

; If the second argument to the setMem macro is 0, the macro
; writes register zero t0 to the memory location. For any other
; value of the second argument, the macro loads the value into t0
; and stores it.

setMem      macro   loc,val         ; loc is a direct page memory
                                    ; location, and val is an
                                    ; 8-bit value to add to that
                                    ; location.
            if      val = 0
            sw      zero, loc
            else
            addi    t0, zero, val
            sb      t0, loc
            endif
            endm

            module  addWithMacro
            rseg    CODE:CODE

addSome     setMem  0xa0(zero),0    ; Set 0 to memory loc. 0xa0.
            setMem  0xa0(zero),1    ; Set 1 to the same address.
            setMem  0xa0(zero),47   ; Set 47 to the same address.
            ret
            end