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IAR Embedded Workbench for RISC-V 3.40

‑‑core

In this section:
Syntax
‑‑core=RV32{E|G|I}[M][A][F][D][C][B][P][N][_NamedExt[_NamedExt1…]]
‑‑core=RV64{G|I}[M][A][F][D][C][B][P][N][_NamedExt[_NamedExt1…]]
Parameters

RV32

Generates code for 32-bit RISC-V devices

RV64

Generates code for 64-bit RISC-V devices

E

Supports the RV32E Base Integer Instruction Set

G

Supports the RV32I/RV64I Base Integer Instruction Set and the M, A, F, and D extensions.

I

Supports the RV32I/RV64I Base Integer Instruction Set

M

Supports the Standard Extension for Integer Multiplication and Division (M)

A

Supports the Standard Extension for Atomic Instructions (A)

F

Supports the Standard Extension for Single-Precision Floating-Point (F)

D

Supports the Standard Extension for Double-Precision Floating-Point (D)

C

Supports the Standard Extension for Compressed Instructions (C)

B

Supports the Standard Extension for Bit Manipulation Instructions (B). This implicitly includes the extensions Zba, Zbb, and Zbs.

P

Supports the proposed Standard Extension for Packed-SIMD Instructions (P), up to version 0.9.11.

N

Supports the Standard Extension for User-Level Interrupts (N)

NamedExt

Supports the named extension. Standard extensions begin with a Z and non-standard extensions with an X. Use underscores to separate multiple extensions. For a list of supported named extensions, see the table below.

Named extension

Description

Xandesdsp

AndeStar™ DSP

Xandesperf

AndeStar™ V5 Performance

Xbcountzeroes

A subset of the standard extension Zbb with count leading/trailing zero instructions

Xcodense

AndeStar™ V5 CoDense extension for code size compaction)

Xeswindsp

Eswin DSP extension. This corresponds to version 0.9.11 of the P extension, although some instructions use the encoding of version 0.9.6.

Xxldsp

Nuclei DSP extension. This corresponds to version 0.5.4 of the P extension and the Xxldsp custom instructions.

Zba

“Base” bit manipulation instructions)

Zbb

“Best of” bit manipulation instructions

Zbc

“Carry-less” bit manipulation instructions

Zbkb

Bit manipulation instructions for cryptography

Zbkc

“Carry-less” multiply instructions

Zbkx

“Cross-bar” permutation instructions

Zbpbo

A subset of bit manipulation instructions required by the P extension

Zbs

“Single bit” bit manipulation instructions

Zcb

Basic code size assembler instructions

Zcmp

Instructions to push and pop multiple registers

Zdinx

Double-precision floating-point instructions that operate on the integer (x) registers

Zfinx

Single-precision floating-point instructions that operate on the integer (x) registers

Zicbom

Cache block management operations

Zicbop

Cache block prefetch operations

Zicboz

Cache block zero operations

Zkne

AES encryption instructions

Zknd

AES decryption instructions

Zknh

SHA2 hash function instructions

Zksed

SM4 block cipher instructions

Zksh

SM3 hash function instructions

Zkn

NIST Algorithm Suite. Equivalent to Zbkb_Zbkc_Zbkx_Zkne_Zknd_Zkn

Zks

ShangMi Algorithm Suite. Equivalent to Zbkb_Zbkc_Zbkx_Zksed_Zks

Zpsfoperand

A subset of P extension instructions for accessing register pairs—optional on RV32, mandatory on RV64

Zpn

The remaining P extension instructions that are not included in Zbpbo or Zpsfoperand)

Legal subset combinations of the P extension:

  • Zpn + Zbpbo (on RV32 but not on RV64)

  • Zpn + Zbpbo + Zpsfoperand

Table 75. Supported named extensions 


Description

Use this option to select the instruction set architecture (ISA) for which the code will be generated. If you do not use this option, the compiler generates code for RV32IM. Note that all modules of your application must use the same parameters.

Single letter parameters that correspond to non-supported standard extensions are accepted but ignored.

The version can be specified after each extension on the form of a major version number, a minor version number, and a subversion number, each number separated by a P, as described in the chapter ISA Subset Naming Conventions in The RISC-V Instruction Set Manual. Volume I: User-Level ISA. Including the subversion number is an IAR-specific extension, required to distinguish between, for example, 0.5.2 and 0.5.4 of the draft P extension. Because the letter P is used both as an extension and as the separator in version numbers, you should use underscores (_) before the extensions to ensure that the specified core string is not ambiguous, for example RV32IC1P2_P2.

Note

The IAR tools do not support all versions of all extensions.

See also

The linker option ‑‑core, ‑‑core.

Caution

Project>Options>General Options>Target