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IAR Debug Probes

Model specifications

In this section:

These are the specifications of I-jet Trace:

USB speed 

4.8 Gbps (USB 3 SuperSpeed)

480 Mbps (USB 2.0 Hi-Speed)

USB connection 

USB 3 Micro-B (USB 2.0 Micro-B-compatible)

Target connection 

MIPI-20 (ETM, JTAG, cJTAG, SWO, SWD, and N-Trace)

MIPI-10 (JTAG, cJTAG, SWO, and SWD)

ARM-20 (JTAG, cJTAG, SWO, and SWD)

Mictor-38 (I-jet Trace A/R/M only) (ETM, JTAG, cJTAG, SWO, SWD, and N-Trace)

External DC power input

5 V DC, 2 A, 0.05 in x 0.14 in (1.3 mm× 3.5 mm)

(Not supplied with I-jet Trace CM)

Debug interface 

ETM, JTAG, cJTAG, SWO, SWD, and N-Trace

JTAG/SWD/cJTAG maximum clock 

100 MHz

JTAG/SWD clock rise and fall time

<= 2 ns

Maximum trace clock

I-jet Trace CM: 150 MHz

SWO protocols supported 

Manchester and UART

SWO sampling frequency

200 MHz

SWO maximum bandwidth 

60 Mbps

Trace memory size

I-jet Trace CM: up to 256 Mbytes

I-jet Trace A/R/M: up to 1 Gbyte

Power supplied to target (4.1 V–4.6 V)

400 mA max with USB 3 ports

200 mA with USB 2 ports

400 mA with External DC power

600 mA (I-jet Trace A/R/M only)

Over-current protection 

~420 mA with USB 3

~220 mA with USB2

~620 mA with External DC power (5 V at 2 A)

Target power measurement resolution 

~160 uA

Target power measurement speed 

up to 200 ksps (kilo samples per second)

JTAG/SWD/trace voltage range 

1.2 V to 5 V

Current draw from VTref 

< 50 uA

Power requirement

3000 mW maximum (from USB or external DC, without target)

Operating temperature 

32–86°F (0–30°C)

Storage temperature 

32–176°F (0–80°C)

I-Jet Trace A/R/M features

In addition to the above model specifications, I-jet Trace A/R/M has these features:

  • Support for ETMv3, ETMv4, and PTM/PFT trace and debug interfaces on any Arm Cortex-A/R/M device equipped with CoreSight

  • Trace port support of up to 350 MHz double data rate (DDR) (700 Msamples/s for each trace data line) for a total of 11.2 Gbit/s throughput

  • Support for streaming of trace data at up to 3.2 Gbytes/s

  • Automatic alignment of parallel trace data skew on individual bits to compensate for PCB layout and signal integrity problems

  • Automatic trace data and clock voltage threshold adjustments to get the most reliable trace data collection with noisy or unterminated target boards

  • 64-bit timestamp with 5 ns resolution (or CPU cycle accurate) for precise timing analysis

  • 16-bit wide trace for Arm devices

  • No external power adapter needed when powering target boards that take less than 200 mA