Interrupt functions for Cortex-M devices
Cortex-M has a different interrupt mechanism than previous Arm architectures, which means the primitives provided by the compiler are also different.
Interrupts for Cortex-M
On Cortex-M, an interrupt service routine enters and returns in the same way as a normal function, which means no special keywords are required. Therefore, the keywords __irq, __fiq, and __nested are not available when you compile for Cortex-M.
These exception function names are defined in cstartup_M.c and cstartup_M.s. They are referred to by the library exception vector code:
NMI_Handler HardFault_Handler MemManage_Handler BusFault_Handler UsageFault_Handler SVC_Handler DebugMon_Handler PendSV_Handler SysTick_Handler
The vector table is implemented as an array. It should always have the name __vector_table, because the C-SPY debugger looks for that symbol when determining where the vector table is located.
The predefined exception functions are defined as weak symbols. A weak symbol is only included by the linker as long as no duplicate symbol is found. If another symbol is defined with the same name, it will take precedence. Your application can therefore simply define its own exception function by just defining it using the correct name from the list above. If you need other interrupts or other exception handlers, you must make a copy of the cstartup_M.c or cstartup_M.s file and make the proper addition to the vector table.
The intrinsic functions __get_CPSR and __set_CPSR are not available when you compile for Cortex-M. Instead, if you need to get or set values of these or other registers, you can use inline assembler. For more information, see Passing values between C and assembler objects.
Interrupts for Cortex-M with FPU
For a Cortex-M core with an FPU, the system register bit FPCCR.ASPEN must be set to 1 to enable automatic state preservation of floating point registers (S0–S15 and FPSCR). This will make interrupt service routines enter and return in the same way as normal functions also when floating-point registers are used.
The floating-point context saving procedure (FPCCR.ASPEN=0) can be omitted when:
only one application task, and no interrupt handler, is going to use the FPU, or
no application task, and only one interrupt handler, is going to use the FPU.
An application running without an operating system is regarded as one single application task. All handlers are affected, including the SVC_Handler, so software interrupt functions (functions declared with the __svc keyword) are also affected.