This is the default strategy. It does whatever is the best way to reset the target device, which for most devices is the same as the reset strategy Core and peripherals (8). Some special handling might be needed for certain devices, for example devices which have a ROM bootloader that needs to run after reset and before your application is started.

Resets the core via the VECTRESET bit—the peripheral units are not affected.

Resets the core and the peripherals.

J-Link pulls its RESET pin low to reset the core and the peripheral units. Normally, this causes the CPU RESET pin of the target device to go low as well, which results in a reset of both the CPU and the peripheral units.

J-Link connects to the target while keeping Reset active (reset is pulled low and remains low while connecting to the target). This is the recommended reset strategy for STM32 devices. This strategy is only available for STM32 devices.

NXP Cortex-M0 devices. This is the same strategy as the Normal strategy, but the target is halted when the bootloader has finished executing. This is the recommended reset strategy for LPC11xx and LPC13xx devices.

Analog Devices Cortex-M3 devices (7), Resets the core and peripheral units by setting the SYSRESETREQ bit in the AIRCR. The core is allowed to perform the ADI kernel (which enables the debug interface) but the core is halted before the first instruction after the kernel is executed to guarantee that no user application code is performed after reset.

This is the same strategy as the Normal strategy, but the target is halted before the bootloader has started executing. This strategy is normally not used, except in situations where the bootloader needs to be debugged. This strategy is only available for LPC11xx and LPC13xx devices.

First performs a Normal reset, to reset the core and peripheral units and halt the CPU immediately after reset. After the CPU is halted, the watchdog is disabled, because the watchdog is by default running after reset. If the target application does not feed the watchdog, J-Link loses connection to the device because it is permanently reset. This strategy is available for Freescale Kinetis devices (6), for NXP LPC 1200 devices (9), and for Samsung S3FN60D devices (10).

Specify the delay between the hardware reset and the halt of the processor. This is used for making sure that the chip is in a fully operational state when C-SPY starts to access it. By default, the delay is set to zero to halt the processor as quickly as possible.

This is a hardware reset.

After reset, J-Link continuously tries to halt the CPU using a breakpoint. Typically, this halts the CPU shortly after reset—in most systems, the CPU can execute some instructions before it is halted.

This is a hardware reset.

Halts the processor by placing a breakpoint at the address zero. Note that this is not supported by all Arm microcontrollers.

This is a hardware reset.

After reset, J-Link continuously tries to halt the CPU using DBGRQ. Typically, this halts the CPU shortly after reset—in most systems, the CPU can execute some instructions before it is halted.

This is a hardware reset.

Sets PC to the program entry address.

This is a software reset.

Uses a reset sequence specific for the Analog Devices ADuC7xxx family. This strategy is only available if you have selected such a device from the Device drop-down list on the General Options>Target page.

This is a software reset.

This strategy is only available if you have selected such a device from the Device drop-down list on the General Options>Target page.

This is a hardware reset specific to NXP LPC devices.

This strategy is only available if you have selected such a device from the Device drop-down list on the General Options>Target page.

This is a hardware reset specific for the Atmel AT91SAM7 family.

Automatically uses the highest possible frequency for reliable operation. The initial speed is the fixed frequency used until the highest possible frequency is found. The default initial frequency—1000 kHz—can normally be used, but in cases where it is necessary to halt the CPU after the initial reset, in as short time as possible, the initial frequency should be increased. If the CPU starts at a low clock speed, you might need to set a lower initial value, for example 32 kHz.

A high initial speed is necessary, for example, when the CPU starts to execute unwanted instructions—for example power down instructions—from flash or RAM after a reset. A high initial speed would in such cases ensure that the debugger can quickly halt the CPU after the reset.

The initial value must be in the range 1–50000 kHz.

Sets the JTAG communication speed in kHz. The value must be in the range 1–50000 kHz.

If there are JTAG communication problems or problems in writing to target memory (for example during program download), these problems might be resolved if the speed is set to a lower frequency.

Synchronizes the clock to the processor clock outside the core. Works only with Arm devices that have the RTCK JTAG signal available. For information about adaptive speed, see the J-Link/J-Trace documentation available at www.segger.com .

Specifies the exact clock frequency used by the internal processor clock, HCLK, in MHz. The value can have decimals. This value is used for configuring the SWO communication speed and for calculating timestamps.

Specifies the clock frequency of the SWO communication channel in kHz.

Automatically uses the highest possible frequency that the debug probe can handle. If Auto is not selected, the wanted SWO clock value can be input in the text box. The value can have decimals. Use this option if data packets are lost during transmission.