I-jet : Setup

Reset

Selects the reset strategy to be used when the debugger starts. Choose between:

Disabled (no reset): No reset is performed.

Software

Sets PC to the program entry address.

This is a software reset.

Hardware

The probe toggles the nSRST/nRESET line on the JTAG connector to reset the device. Usually, this reset also resets the peripheral units.

The processor should stop at the reset handler before executing any instruction. Some processors might not stop at the reset vector, but will be halted soon after, executing some instructions.

Core

Resets a single core in a multicore system using the hartreset bit. This strategy is optional according to the RISC-V debug specification. Because it is optional, a software reset will be performed if hardware support is missing.

Only available for some devices.

System

Resets all harts of the processor using the dmcontrol.ndmreset bit. On some devices, it might reset more components—exactly what is affected by this reset is device-dependent.

This strategy is mandatory according to the RISC-V debug specification.

All strategies halt the CPU after the reset.

A software reset of the target does not change the settings of the target system—it only resets the program counter and the mode register to its reset state.

Normally, a C-SPY reset is only a software reset. If you use the Hardware option, C-SPY will generate an initial hardware reset when the debugger is started. This is performed once before download, and if the option Use flash loader(s) is selected, also once after flash download.

Tip

Hardware resets can be a problem if the low-level setup of your application is not complete. If the low-level setup does not set up memory configuration and clocks, the application will not work after a hardware reset. To handle this in C-SPY, the setup macro function execUserReset() is suitable.

Duration

The time in milliseconds that the hardware reset asserts the reset signal (line nSRST/nRESET) low to reset the device.

Some devices might require a longer reset signal than the default 300 ms.

This option applies to the hardware reset, and to those custom reset strategies that use the hardware reset.

Override default delay after reset

Use this option to change the default delay time, in milliseconds, after the reset signal has been de-asserted, before the debugger attempts to control the processor.

The processor might be kept internally in reset for some time after the external reset signal has been de-asserted, and thus inaccessible for the debugger.

This option applies to the hardware reset, and to those custom reset styles that use the hardware reset.

Target power

These options specify how the target system is powered, and if it is powered from the debug probe, the status of the power supply after debugging.

From the probe: Supplies the target system with power from the probe. If this option is deselected, the target system must be powered separately.

Leave on after debugging: Continues to supply the target system with power from the probe even after the debug session has been stopped.

Switch off after debugging: Turns off the power to the target when the debug session stops.

Emulator

These options are used for identifying the debug probe to use.

Always prompt for probe selection: Makes C-SPY always ask you to confirm which probe to use, if more than one debug probe is connected to the host computer.

Serial no: Enter the serial number of the debug probe you are using.

Allow system bus access

Informs the C-SPY driver that the target device supports memory access via the system bus. This is required for Live Watch and live updates of the Memory windows.

Log communication

Logs the communication between C-SPY and the target system to a file. To interpret the result, detailed knowledge of the interface is required.

IAR Embedded Workbench for RISC-V 3.40